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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145159-1/D
MC145159-1 Serial-Input PLL Frequency Synthesizer with Analog Phase Detector
Interfaces with Dual-Modulus Prescalers
The MC145159-1 has a programmable 14-bit reference counter, as well as fully programmable divide-by-N/divide-by-A counters. The counters are programmed serially through a common data input and latched into the appropriate counter latch, according to the last data bit (control bit) entered. When combined with a loop filter and VCO, this device can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operations, a down mixer or a dual-modulus prescaler can be used between the VCO and the PLL. * * * * * * * * * Operating Temperature Range: - 40 to 85C Low Power Consumption Through Use of CMOS Technology 3.0 to 9.0 V Supply Range On- or Off-Chip Reference Oscillator Operation Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs / R Range = 3 to 16383 / N Range = 16 to 1023, / A Range = 0 to 127 High-Gain Analog Phase Detector See Application Note AN969
20 1
20 1
P SUFFIX PLASTIC DIP CASE 738
DW SUFFIX SOG PACKAGE CASE 751D
VF SUFFIX SSOP CASE TBD
ORDERING INFORMATION
MC145159P1 MC145159DW1 MC145159VF1 Plastic DIP SOG Package SSOP
PIN ASSIGNMENTS PLASTIC DIP AND SOG PACKAGE
RO OSCin OSCout CHARGE VDD FSO VSS MC LD fin 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RR VDD CH APDout VSS CR SRout ENB DATA CLK VSS APDout CH VDD RR RO OSCin OSCout CHARGE VDD 1 2 3 4 5 6 7 8 9 10
SSOP
20 19 18 17 16 15 14 13 12 11 CR SRout ENB DATA CLK fin LD MC VSS FSO
REV 1 8/95
(c) Motorola, Inc. 1995 MOTOROLA
MC145159-1 1
BLOCK DIAGRAM
ENB OSCout 14-BIT LATCH OSCin 14-BIT / R COUNTER fV CONTROL LOGIC fin 7-BIT / A COUNTER 7-BIT LATCH DATA CLK 1-BIT S/R 7-BIT S/R 10-BIT / N COUNTER 10-BIT LATCH 10-BIT S/R LOCK DETECTOR LD DIGITAL FREQUENCY STEERING fR ANALOG PHASE DETECTOR
14-BIT S/R
SRout CHARGE CH RR RO CR APDout VDD VSS MC FSO
* FSO is not and cannot be used as a digital phase detector output.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Vin, Vout Iin, Iout IDD, ISS PD Tstg TL Parameter DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Supply Current, VDD or VSS Pins Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) Value - 0.5 to + 10 - 0.5 to VDD + 0.5 10 30 500 - 65 to + 150 260 Unit V V mA mA mW C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
* Maximum Ratings are those values beyond which damage to the device may occur.
MC145159-1 2
MOTOROLA
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS except ICR and IAPD which are referenced to VSS)
- 40C Characteristic Ch ii Power Supply Voltage Range Output Voltage Vin = 0 V or VDD Iout = 0 A (Except OSCout and APDout) 0 Level Symbol S bl VDD VOL VDD -- 3 5 9 3 5 9 3 5 9 3 5 9 -- 3 5 9 3 5 9 3 5 9 VIH 3 5 9 IOH Source 3 5 9 IOL 3 5 9 9 9 - 0.60 - 0.90 - 1.50 1.30 1.90 3.80 -- -- -- -- -- -- -- -- -- -- - 0.50 - 0.75 - 1.25 1.10 1.70 3.30 - 90 170 -- -- -- -- -- -- - 110 350 - 0.30 - 0.50 - 0.80 0.66 1.08 2.10 -- -- -- -- -- -- -- -- -- -- A A mA 3 5 9 IOL 3 5 9 9 9 -- -- 3 5 9 9 - 0.44 - 0.64 - 1.30 0.44 0.64 1.30 -- 2 -- -- -- -- -- -- -- -- -- -- -- -- 0.3 50 10 10 800 1200 1600 0.3 - 0.35 - 0.51 - 1.00 0.35 0.51 1.00 -- 2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 25 10 10 800 1200 1600 0.1 - 0.22 - 0.36 - 0.70 0.22 0.36 0.70 -- 2 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 22 10 10 1600 2400 3200 3.0 A A pF pF A 3.0 5.0 9.0 -- -- -- 3.0 5.0 9.0 -- -- -- 3.0 5.0 9.0 -- -- -- mA Min 3 -- -- -- 2.95 4.95 8.95 -- -- -- 2.1 3.5 6.3 -- -- -- -- 2.1 3.5 6.3 -- -- -- Max 9 0.05 0.05 0.05 -- -- -- 0.9 1.5 2.7 -- -- -- -- 0.9 1.5 2.7 -- -- -- 0 0 0 Min 3 -- -- -- 2.95 4.95 8.95 -- -- -- 2.1 3.5 6.3 -- -- -- -- 2.1 3.5 6.3 -- -- -- 25C Max 9 0.05 0.05 0.05 -- -- -- 0.9 1.5 2.7 -- -- -- 1.05 0.9 1.5 2.7 -- -- -- 0 0 0 Min 3 -- -- -- 2.95 4.95 8.95 -- -- -- 2.1 3.5 6.3 -- -- -- -- 2.1 3.5 6.3 -- -- -- 85C Max 9 0.05 0.05 0.05 -- -- -- 0.9 1.5 2.7 -- -- -- -- 0.9 1.5 2.7 -- -- -- V 0 0 0 V V V V Unit Ui V V
1 Level
VOH
Output Voltage OSCout Vin = 0 V or VDD
0 Level
VOL
1 Level
VOH
Voltage, VCH - VAPDout, IAPDout 0 A Input Voltage Vout = 0.5 V or VDD - 0.5 V (All Outputs Except OSCout) 0 Level
V VIL
1 Level
VIH
Input Voltage* -- OSCin VO = 2.1 V or 0.9 V VO = 3.5 V or 1.5 V VO = 6.3 V or 2.7 V VO = 0.9 V or 2.1 V VO = 1.5 V or 3.5 V VO = 2.7 V or 6.3 V Output Current -- MC Vout = 2.7 V Vout = 4.6 V Vout = 8.5 V Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V Output Current, CR, VCR = 4.5 V, RR = 240 k Output Current, APDout RO = 240 k, VCH = 0 V, VAPDout = 4.5 V Output Current -- Other Outputs Vout = 2.7 V Vout = 4.6 V Vout = 8.5 V Vout = 0.3 V Vout = 0.4 V Vout = 0.5 V Input Current -- Data, CLK, ENB Input Current -- fin, OSCin Input Capacitance Three-State Output Capacitance -- FSO Quiescent Current Vin = 0 V or VDD Iout = 0 A Three-State Leakage Current, Vout = 0 V or 9 V * dc coupled square wave.
VIL 0 Level
1 Level
Sink
ICR IAPD IOH Source
Sink
Iin Iin Cin Cout IDD
IOZ
A
MOTOROLA
MC145159-1 3
SWITCHING CHARACTERISTICS (TA = 25C, CL = 50 pF)
Characteristic Output Rise Time -- MC Figure No. 4, 9 Symbol tTLH VDD 3 5 9 3 5 9 3 5 9 3 5 9 3 5 9 3 5 9 6 th 3 5 9 3 5 9 3 5 9 3 5 9 Min -- -- -- -- -- -- -- -- -- -- -- -- 30 20 18 70 32 25 12 12 15 5 10 20 -- -- -- 40 35 25 Max 115 60 40 60 34 30 140 80 60 125 80 50 -- -- -- -- -- -- -- -- -- -- -- -- 5 2 0.5 -- -- -- ns Unit ns
Output Fall Time -- MC
4, 9
tTHL
ns
Output Rise and Fall Time -- LD and SRout
4, 9
tTLH, tTHL tPLH, tPHL tsu
ns
Propagation Delay Time -- fin to MC
5, 9
ns
Setup Times -- Data to CLK
6
ns
CLK to ENB
Hold Time -- CLK to Data
Recovery Time -- ENB to CLK
6
trec
ns
Input Rise and Fall Times -- CLK, OSCin, fin
7
tr, tf
s
Input Pulse Width -- ENB and CLK
8
tw
ns
NOTE: Refer to the graphs and text in application note AN969 for maximum frequency information.
MC145159-1 4
MOTOROLA
PIN DESCRIPTIONS
INPUT PINS OSCin, OSCout Oscillator Input and Oscillator Output (PDIP, SOG - Pins 2, 3; SSOP - Pins 7, 8) These pins form an on-chip reference oscillator when connected to terminals of an external parallel-resonant crystal. Frequency-setting capacitors of appropriate value must be connected from OSC in to V SS and OSC out to V SS. OSC in may also serve as input for an externally-generated reference signal. This signal will typically be ac coupled to OSC in, but for larger amplitude signals (standard CMOS logic levels), dc coupling may also be used. In the external reference mode, no connection is required to OSC out . fin Frequency Input (PDIP, SOG - Pin 10, SSOP - Pin 15) Input to the positive edge triggered divide-by-N and divide-by-A counters. fin is typically derived from a dual- modulus prescaler and is ac coupled. This input has an inverter biased in the linear region to allow use with ac coupled signals as low as 500 mV peak-to-peak or direct coupled signals swinging from VDD to VSS. DATA Serial Data Input (PDIP, SOG - Pin 12, SSOP - Pin 17) Counter and control information is shifted into this input. The last data bit entered goes into the one-bit control shift register. A logic 1 allows the reference counter information to be loaded into its 14-bit latch when ENB goes high. A logic 0 entered as the control bit disables the reference counter latch. The divide-by-A/divide-by-N counter latch is loaded, regardless of the contents of the control register, when ENB goes high. The data entry format is shown in Figure 1. ENB Transparent Latch Enable (PDIP, SOG - Pin 13, SSOP - Pin 18) A logic high on this input allows data to be entered into the divide-by-A/divide-by-N latch and, if the control bit is high, into the reference counter latch. Counter programming is unaffected when ENB is low. ENB should be kept normally low and pulsed high to transfer data to the latches. CLK Shift Register Clock (PDIP, SOG - Pin 11, SSOP - Pin 16) A low-to-high transition on this input shifts data from the serial data input into the shift registers.
COMPONENT PINS CR Ramp Capacitor (PDIP, SOG - Pin 15, SSOP - Pin 20) The capacitor connected from this pin to VSS is charged linearly, at a rate determined by RR. The voltage on this capacitor is proportional to the phase difference of the frequencies present at the internal phase detector inputs. A polystyrene or mylar capacitor is recommended. RR Ramp Current Bias Resistor (PDIP, SOG - Pin 20, SSOP - Pin 5) A resistor connected from this pin to VSS determines the rate at which the ramp capacitor is charged, thereby affecting the phase detector gain (see Figure 2). CH Hold Capacitor (PDIP, SOG - Pin 18, SSOP - Pin 3) The charge stored on the ramp capacitor is transferred to the capacitor connected from this pin to either VDD or VSS. The ratio of CR to CH should be large enough to have no effect on the phase detector gain (CR > 10 CH). A low-leakage capacitor should be used. RO Output Bias Current Resistor (PDIP, SOG - Pin 1, SSOP - Pin 6) A resistor connected from this pin to VSS biases the output N-Channel transistor, thereby setting a current sink on the analog phase detector output. This resistor adjusts the APDout bias current (see Figure 3). OUTPUT PINS APDout Analog Phase Detector Output (PDIP, SOG - Pin 17, SSOP - Pin 2) This output produces a voltage that controls an external VCO. The voltage range of this output (V DD = + 9 V) is from below + 0.5 V to + 8 V or more. The source impedance of this output is the equivalent of a source follower with an externally variable source resistor. The source resistor depends upon the output bias current controlled by the output bias current resistor, RO. The bias current is adjustable from 0.01 mA to 0.5 mA. The output voltage is not more than 1.05 V below the sampled point on the ramp. With a constant sample of the ramp voltage at 9 V and the hold capacitor of 50 pF, the instantaneous output ripple is about 5 mV peak- to-peak.
LATCHED WHEN CONTROL BIT = 1 SHIFT REGISTER OUT
DATA IN
LAST BIT
A0 LSB
A6 MSB
N0 LSB
N9 MSB
R0 LSB
R13 MSB
CONTROL BIT
LATCHED WHEN CONTROL BIT = 0
Figure 1. Data Entry Format
MOTOROLA
MC145159-1 5
CHARGE Ramp Charge Indicator (PDIP, SOG - Pin 4, SSOP - Pin 9) This output is high from the time fR goes high to the time fV goes high (fR and fV are the frequencies at the phase detector inputs). This high voltage indicates that the ramp capacitor, CR, is being charged. FSO Three-State Frequency Steering Output (PDIP, SOG - Pin 6, SSOP - Pin 11) If the counted down input frequency on fin is higher than the counted down reference frequency of OSCin, this output goes low. If the counted down VCO frequency is lower than that of the counted down OSCin, this output goes high. The repetition rate of the frequency steering output pulses is approximately equal to the difference of the frequencies of the two counted down inputs from the VCO and OSCin. See Application Note AN969 for further information. LD Lock Detector Indicator (PDIP, SOG - Pin 9, SSOP - Pin 14) This output is high during lock and goes low to indicate a non-lock condition. The frequency and duration of the non- lock pulses will be the same as either polarity of the frequency steering output. MC Dual Modulus Prescaler Control (PDIP, SOG - Pin 8, SSOP - Pin 13) The modulus control level is low at the beginning of a count cycle and remains low until the divide-by-A counter has counted down from its programmed value. At that time, the modulus control goes high and remains high until the divide-by-N counter has counted the rest of the way down from its programmed value (N - A additional counts since both divide-by-N and divide-by-A are counting down during the first portion of the cycle). Modulus control is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value of NT = N P + A, where P
and P + 1 represent the dual modulus prescaler divide values respectively for high and low modulus control levels, N is the number programmed into the divide-by-N counter, and A is the number programmed into the divide-by-A counter. SRout Shift Register Output (PDIP, SOG - Pin 14, SSOP - Pin 19) This pin is the non-inverted output of the last stage of the 32-bit serial data shift register. It is not latched by the ENB line. If unused, SRout should be floated. POWER SUPPLY VDD Positive Power Supply (PDIP, SOG - Pin 5, SSOP - Pin 10) Positive power supply input for all sections of the device except the analog phase detector. VDD and VDD should be powered up at the same time to avoid damage to the MC145159-1. VDD must be tied to the same potential as VDD. VSS Negative Power Supply (PDIP, SOG - Pin 7, SSOP - Pin 12) Circuit ground for all sections of the MC145159-1 except the analog phase detector. VSS must be tied to the same potential as VSS. VSS Analog Phase Detector Circuit Ground (PDIP, SOG - Pin 16, SSOP - Pin 1) Separate power supply and ground inputs are provided to help reduce the effects in the analog section of noise coming from the digital sections of this device and the surrounding circuitry. VDD Analog Power Supply (PDIP, SOG - Pin 19, SSOP - Pin 4) Separate power supply and ground inputs are provided to help reduce the effects in the analog section of noise coming from the digital sections of this device and the surrounding circuitry.
MC145159-1 6
MOTOROLA
700
500 V =3V DD 300 200 5V 9V
, ANALOG OUTPUT BIAS CURRENT (mA) APD
1000
V = 0 V, V = 0.5 V CH APD DD
, RAMP RESISTANCE (k
)
6.0
5.0
4.0
V DD
=9V
100 70 50
3.0
2.0
R
R
30 20
1.0
V DD
=5V
20 30 50 70 100 200 300 500 700 1000
10 3 5 7 10 20 30 50 70 100 200 300 500 1k 2k 3k
10
I , CHARGE CURRENT (A) CHARGE
I
R , OUTPUT RESISTANCE (k) O
Figure 2. Charge Current vs Ramp Resistance
Figure 3. APDout Bias Current vs Output Resistance
DESIGN EQUATION
K = ICHARGE 2 fRCR
where K = phase detector gain, ICHARGE is from Figure 2 fR = reference frequency CR = ramp capacitor (in farads)
SWITCHING WAVEFORMS
V DD t TLH ANY OUTPUT 10% 90% t PLH t PHL t THL f in 50% V SS
MC
50%
Figure 4. Figure 5.
V DATA 50% V SS t su t h V CLK 50% LAST CLOCK t su t rec V ENB 50% V SS PREVIOUS DATA LATCHED DD FIRST CLOCK V SS DD CLK OSC , f in in t r 90% 10% t f V DD DD
V SS
Figure 7.
Figure 6.
DEVICE UNDER t w V ENB, CLK 50% V SS DD TEST
OUTPUT
C L*
* Includes all probe and fixture capacitance.
Figure 8.
Figure 9. Test Circuit
MOTOROLA
MC145159-1 7
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers. Use of a Hybrid Crystal Oscillator Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing 50 A at CMOS logic levels may be direct or dc coupled to OSC in. In general, the highest frequency capability is obtained utilizing a direct coupled square wave having a rail-to-rail (V DD to V SS) voltage swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSC in may be used. OSC out , an unbuffered output, should be left floating. For additional information about TCXOs and data clock oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar publications. Design an Off-Chip Reference The user may design an off-chip crystal oscillator using ICs specifically developed for crystal oscillator applications, such as the MC12061 MECL device. The reference signal from the MECL device is ac coupled to OSC in. For large amplitude signals (standard CMOS logic levels), dc coupling is used. OSC out, an unbuffered output, should be left floating. In general, the highest frequency capability is obtained with a direct-coupled square wave having rail-to-rail voltage swing. Use of the On-Chip Oscillator Circuitry The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 10. For VDD = 5 V, the crystal should be specified for a loading capacitance, CL, which does not exceed 32 pF for frequencies to approximately 8 MHz, 20 pF for frequencies in the area of 8 to 15 MHz, and 10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic CL values. Assuming R1 = 0 . the shunt load capacitance, CL, presented across the crystal can be estimated to be: CL = CinCout + Ca + Cstray + C1 * C2 C1 + C2 Cin + Cout where Cin = 5 pF (see Figure 11) Cout = 6 pF (see Figure 11) Ca = 1 pF (see Figure 11) C1 and C2 = external capacitors (see Figure 10) Cstray = the total equivalent external circuit stray capacitance appearing across the crystal terminals The oscillator can be "trimmed" on-frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSC out pins to minimize distortion, stray capacitance,
stray inductance, and start-up stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value to the values for Cin and Cout. For this approach, the term Cstray becomes zero in the above expression for CL. Power is dissipated in the effective series resistance of the crystal, Re, in Figure 12. The maximum drive level specified by the crystal manufacturer represents the maximum stress that a crystal can withstand without damaging or excessive shift in operating frequency. R1 in Figure 10 limits the drive level. The use of R1 is not necessary in most cases. To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at OSCout. (Care should be taken to minimize loading.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful. See Table 1.
Rf FREQUENCY SYNTHESIZER
OSCin
R1*
OSCout
C1
C2
* May be deleted in certain cases. See text.
Figure 10. Pierce Crystal Oscillator Circuit
Ca OSCin Cin Cstray Cout OSCout
Figure 11. Parasitic Capacitances of the Amplifier and Cstray
RS 1 2 1 LS CS 2
CO 1 Re Xe 2
NOTE: Values are supplied by crystal manufacturer (parallel resonant crystal).
Figure 12. Equivalent Crystal Networks
MC145159-1 8
MOTOROLA
Table 1. Partial List of Crystal Manufacturers
Name United States Crystal Corp. Crystek Crystal Statek Corp. Address 3605 McCart Ave., Ft. Worth, TX 76110 2351 Crystal Dr., Ft. Myers, FL 33907 512 N. Main St., Orange, CA 92668 Phone (817) 921-3013 (813) 936-2109 (714) 639-7810
NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers.
RECOMMENDED READING
Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. E. Hafner, "The Piezoelectric Crystal Unit - Definitions and Method of Measurement", Proc. IEEE, Vol. 57, No. 2 Feb., 1969. D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969. P. J. Ottowitz, "A Guide to Crystal Selection", Electronic Design, May, 1966. D. Babin, "Designing Crystal Oscillators", Machine Design, March 7, 1985. D. Babin, "Guidelines for Crystal Oscillator Design", Machine Design, April 25, 1985.
fin
fv FEEDBACK (fin
/ N)
fR
REFERENCE (OSC
/ R)
SAMPLE
CHARGE
DISCHARGE
CR
CH
APDout
Figure 13. Timing Diagram for Minimum Divide Value (N = 16)
MOTOROLA
MC145159-1 9
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP (DUAL IN-LINE PACKAGE) CASE 738-03
-ANOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
20
11
B
1 10
2. 3.
CONTROLLING DIMENSION: INCH. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4.
DIMENSION B DOES NOT INCLUDE MOLD FLASH.
C
L
-TSEATING PLANE
K M E G F D 20 PL
0.25 (0.010)
M
N J 20 PL
0.25 (0.010) T A
M M
T
B
M
DIM A B C D E F G J K L M N
INCHES MIN MAX
1.010 0.240 0.150 0.015 1.070 0.260 0.180 0.022
MILLIMETERS MIN MAX
25.66 6.10 3.81 0.39 27.17 6.60 4.57 0.55
0.050 BSC 0.050 0.070
1.27 BSC 1.27 1.77
0.100 BSC 0.008 0.110 0.015 0.140
2.54 BSC 0.21 2.80 0.38 3.55
0.300 BSC 0 0.020 15 0.040
7.62 BSC 0 0.51 15 1.01
DW SUFFIX SOG (SMALL OUTLINE GULL-WING) PACKAGE CASE 751D-04 -A-
20 11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
-B-
1 10
10X
P
0.010 (0.25)
M
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.
B
M
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
20X
D
M
J
T A
S
0.010 (0.25)
B
S
F R C -T-
18X
SEATING PLANE
X 45 _
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX
12.65 7.40 2.35 0.35 0.50 12.95 7.60 2.65 0.49 0.90
INCHES MIN MAX
0.499 0.292 0.093 0.014 0.020 0.510 0.299 0.104 0.019 0.035
1.27 BSC 0.25 0.10 0 0.32 0.25 7
0.050 BSC 0.010 0.004 0 0.012 0.009 7
_
_
_
_
10.05 0.25
10.55 0.75
0.395 0.010
0.415 0.029
G
K
M
MC145159-1 10
MOTOROLA
VF SUFFIX SSOP CASE TBD
PLACE WHEN GET CASE#
MOTOROLA
MC145159-1 11
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MC145159-1 12
*MC145159-1/D*
MC145159-1/D MOTOROLA

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